Difference between revisions of "Icarus Verilog"
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| − | + | {{Package-Introduction|Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog (plus extensions) and generates an internal netlist. The netlist is passed to various processing steps that transform the design to more optimal/practical forms, then passed to a code generator for final output. The processing steps and the code generator are selected by command line switches.|http://www.icarus.com/eda/verilog}} | |
== Dependencies == | == Dependencies == | ||
Revision as of 13:53, 16 April 2007
| Download Source: | ftp://ftp.geda.seul.org/pub/geda/dist/verilog-20070608.tar.gz |
|---|
Contents
Introduction to Icarus Verilog
Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog (plus extensions) and generates an internal netlist. The netlist is passed to various processing steps that transform the design to more optimal/practical forms, then passed to a code generator for final output. The processing steps and the code generator are selected by command line switches.
Project Homepage: http://www.icarus.com/eda/verilog
Dependencies
Recommended
Non-Multilib
Compile the package:
./configure --prefix=/usr && make
Install the package
make install
Install the example files:
install -v -m755 -d /usr/share/doc/verilog/examples && cp -v examples/* /usr/share/doc/verilog/examples
Multilib
32Bit
To do ...
N32
To do ...
64Bit
To do ...
Contents
| Installed Directories: | /usr/lib/ivl |
|---|---|
| Installed Programs: |
iverilog, vvp, iverilog-vpi |
| Installed Libraries: |
libvpi.a, libveriuser.a |
Short Descriptions
| iverilog: | Compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. |
|---|---|
| vvp: | Run time engine that executes the default compiled form generated by Icarus Verilog. |
| iverilog-vpi: | Tool to simplify the compilation of VPI modules for use with Icarus Verilog. |
